1. Field of the Invention
This invention is related to the field of processors and, more particularly, to segment descriptor tables for storing segment descriptors used by the processor.
2. Description of the Related Art
The x86 architecture (also known as the IA-32 architecture) has enjoyed widespread acceptance and success in the marketplace. Accordingly, it is advantageous to design processors according to the x86 architecture. Such processors may benefit from the large body of software written to the x86 architecture (since such processors may execute the software and thus computer systems employing the processors may enjoy increased acceptance in the market due to the large amount of available software).
As computer systems have continued to evolve, 64 bit address size (and sometimes operand size) has become desirable. A larger address size allows for programs having a larger memory footprint (the amount of memory occupied by the instructions in the program and the data operated upon by the program) to operate within the memory space. A larger operand size allows for operating upon larger operands, or for more precision in operands. More powerful applications and/or operating systems may be possible using 64 bit address and/or operand sizes.
Unfortunately, the x86 architecture is limited to a maximum 32 bit operand size and 32 bit address size. The operand size refers to the number of bits operated upon by the processor (e.g. the number of bits in a source or destination operand). The address size refers to the number of bits in an address generated by the processor. Thus, processors employing the x86 architecture may not serve the needs of applications which may benefit from 64 bit address or operand sizes.
One of the reasons that the x86 architecture is limited to 32 bit address size is a segmentation mechanism employed as part of the address translation mechanism. Segment descriptors in a segment table provide a segment base address (of 32 bits) which is added to other operands of an instruction to produce a linear address.
A segment descriptor table is described which stores segment descriptors of different sizes. Smaller segment descriptors may be segment descriptors similar to the x86 architecture definition, and larger segment descriptors may be used to provide virtual addresses (e.g. base addresses or offsets) having more than 32 bits. By providing a segment descriptor table that stores different sized segment descriptors, maintaining multiple segment descriptor tables for different operating modes may be avoidable while providing support for segment descriptors having addresses greater than 32 bits. In one embodiment, the larger segment descriptors may be twice the size of the smaller segment descriptors. The segment descriptor table may comprise entries, each capable of storing the smaller segment descriptor, and a larger segment descriptor may occupy two entries of the table.
Broadly speaking, a memory is contemplated. The memory stores at least one descriptor table storing at least a first segment descriptor and a second segment descriptor. The second segment descriptor is larger than the first segment descriptor. An apparatus including the memory and a processor is also contemplated.
Additionally, a method is contemplated. A first segment descriptor is stored in a segment descriptor table. A second segment descriptor is stored in the segment descriptor table. The second segment descriptor is larger than the first segment descriptor.